(1) Filed of the Invention
The present invention relates generally to semiconductor integrated circuit manufacturing and more particularly to methods and structures for monitoring and controlling overlay and spacing.
(2) Description of Prior Art
As design rules shrink there are increased accuracy requirements for the alignment of features on successive wafer levels and for the separation of features on a single level; i.e. for overlay and spacing. To meet these requirements overlay and spacing need to be monitored and controlled. The prior art includes various electrical test structures and methods for this purpose. Resistive and van der Pauw bridges are used with features whose relative alignment is desired forming elements of the bridge. The bridge test structure is designed so that for exact alignment a null result is obtained; e.g. equal voltages across the features being compared. The degree of misalignment is ascertained by the difference in the voltage measured across the features. Voltages across features are often small, especially when their resistance is low. Differences in voltage across features needed to detect small misalignments are smaller yet. Thus special equipment and techniques are required to achieve the required sensitivity in the voltage measurements. In addition, elaborate test structures, testing procedures and algorithms are needed to extract quantitative misalignment results from measured voltages. Cresswell et al., in U.S. Pat. No. 5,383,136 disclose an electrical test structure and method for measuring the misalignment of conductive features on an insulating substrate. A bridge method is used and misalignment is proportional to the difference in voltage across features being compared. The test structure is designed so that effects of the test structure geometry can be measured and compensated for using a succession of test signals and inserting the measured response voltages in provided algorithms. These elaborate structures and procedures, as well as high precision voltage measurements are required to achieve the fine resolution needed for submicron design rules. U.S. Pat. No. 5,602,492 to Cresswell et al., a continuation-in-part of U.S. Pat. No. 5,383,136, teaches a method of eliminating random errors arising from imperfections. U.S. Pat. No. 5,617,340 to Cresswell et al. and U.S. Pat. No. 5,699,282 to Allen et al. are continuations-in-part of the above patents and involve methods for measuring misalignment, which require a multiplicity of test structures and a multiplicity of precision measurements. Buehler et al. in U.S. Pat. No. 4,918,377 teach a method of determining the reliability of conductors deposited on an uneven surface. The method involves measuring the resistance of a test structure in which the conductors are deposited over a multiplicity of steps.